/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2019-2022. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * Description:
 * Author: huawei
 * Create: 2019-10-15
 */

#ifndef AO_SUBCTRL_REG_OFFSET_FIELD_H
#define AO_SUBCTRL_REG_OFFSET_FIELD_H

#define AO_SUBCTRL_TIMEOUT_INFO_LEN    32
#define AO_SUBCTRL_TIMEOUT_INFO_OFFSET 0

#define AO_SUBCTRL_I2C4_DAT_OE_CFG_LEN     1
#define AO_SUBCTRL_I2C4_DAT_OE_CFG_OFFSET  5
#define AO_SUBCTRL_I2C4_SDA_CFG_LEN        1
#define AO_SUBCTRL_I2C4_SDA_CFG_OFFSET     4
#define AO_SUBCTRL_I2C4_SCL_CFG_LEN        1
#define AO_SUBCTRL_I2C4_SCL_CFG_OFFSET     3
#define AO_SUBCTRL_I2C4_DAT_MUX_SEL_LEN    1
#define AO_SUBCTRL_I2C4_DAT_MUX_SEL_OFFSET 2
#define AO_SUBCTRL_I2C4_CLK_OE_CFG_LEN     1
#define AO_SUBCTRL_I2C4_CLK_OE_CFG_OFFSET  1
#define AO_SUBCTRL_I2C4_CLK_MUX_SEL_LEN    1
#define AO_SUBCTRL_I2C4_CLK_MUX_SEL_OFFSET 0

#define AO_SUBCTRL_I2C5_DAT_OE_CFG_LEN     1
#define AO_SUBCTRL_I2C5_DAT_OE_CFG_OFFSET  5
#define AO_SUBCTRL_I2C5_SDA_CFG_LEN        1
#define AO_SUBCTRL_I2C5_SDA_CFG_OFFSET     4
#define AO_SUBCTRL_I2C5_SCL_CFG_LEN        1
#define AO_SUBCTRL_I2C5_SCL_CFG_OFFSET     3
#define AO_SUBCTRL_I2C5_DAT_MUX_SEL_LEN    1
#define AO_SUBCTRL_I2C5_DAT_MUX_SEL_OFFSET 2
#define AO_SUBCTRL_I2C5_CLK_OE_CFG_LEN     1
#define AO_SUBCTRL_I2C5_CLK_OE_CFG_OFFSET  1
#define AO_SUBCTRL_I2C5_CLK_MUX_SEL_LEN    1
#define AO_SUBCTRL_I2C5_CLK_MUX_SEL_OFFSET 0

#define AO_SUBCTRL_I2C6_DAT_OE_CFG_LEN     1
#define AO_SUBCTRL_I2C6_DAT_OE_CFG_OFFSET  5
#define AO_SUBCTRL_I2C6_SDA_CFG_LEN        1
#define AO_SUBCTRL_I2C6_SDA_CFG_OFFSET     4
#define AO_SUBCTRL_I2C6_SCL_CFG_LEN        1
#define AO_SUBCTRL_I2C6_SCL_CFG_OFFSET     3
#define AO_SUBCTRL_I2C6_DAT_MUX_SEL_LEN    1
#define AO_SUBCTRL_I2C6_DAT_MUX_SEL_OFFSET 2
#define AO_SUBCTRL_I2C6_CLK_OE_CFG_LEN     1
#define AO_SUBCTRL_I2C6_CLK_OE_CFG_OFFSET  1
#define AO_SUBCTRL_I2C6_CLK_MUX_SEL_LEN    1
#define AO_SUBCTRL_I2C6_CLK_MUX_SEL_OFFSET 0

#define AO_SUBCTRL_I2C9_DAT_OE_CFG_LEN     1
#define AO_SUBCTRL_I2C9_DAT_OE_CFG_OFFSET  5
#define AO_SUBCTRL_I2C9_SDA_CFG_LEN        1
#define AO_SUBCTRL_I2C9_SDA_CFG_OFFSET     4
#define AO_SUBCTRL_I2C9_SCL_CFG_LEN        1
#define AO_SUBCTRL_I2C9_SCL_CFG_OFFSET     3
#define AO_SUBCTRL_I2C9_DAT_MUX_SEL_LEN    1
#define AO_SUBCTRL_I2C9_DAT_MUX_SEL_OFFSET 2
#define AO_SUBCTRL_I2C9_CLK_OE_CFG_LEN     1
#define AO_SUBCTRL_I2C9_CLK_OE_CFG_OFFSET  1
#define AO_SUBCTRL_I2C9_CLK_MUX_SEL_LEN    1
#define AO_SUBCTRL_I2C9_CLK_MUX_SEL_OFFSET 0

#define AO_SUBCTRL_SPI5_CS_POLARITY_LEN    1
#define AO_SUBCTRL_SPI5_CS_POLARITY_OFFSET 2
#define AO_SUBCTRL_SPI5_RFT_K3_MODE_LEN    1
#define AO_SUBCTRL_SPI5_RFT_K3_MODE_OFFSET 1
#define AO_SUBCTRL_SPI5_SYN_EN_LEN         1
#define AO_SUBCTRL_SPI5_SYN_EN_OFFSET      0

#define AO_SUBCTRL_LP_WDOG_CLK_SEL_LEN    1
#define AO_SUBCTRL_LP_WDOG_CLK_SEL_OFFSET 0

#define AO_SUBCTRL_WDOG0_CLK_SEL_LEN    1
#define AO_SUBCTRL_WDOG0_CLK_SEL_OFFSET 0

#define AO_SUBCTRL_WDOG1_CLK_SEL_LEN    1
#define AO_SUBCTRL_WDOG1_CLK_SEL_OFFSET 0

#define AO_SUBCTRL_WDOG2_CLK_SEL_LEN    1
#define AO_SUBCTRL_WDOG2_CLK_SEL_OFFSET 0

#define AO_SUBCTRL_WDOG3_CLK_SEL_LEN    1
#define AO_SUBCTRL_WDOG3_CLK_SEL_OFFSET 0

#define AO_SUBCTRL_WDOG4_CLK_SEL_LEN    1
#define AO_SUBCTRL_WDOG4_CLK_SEL_OFFSET 0

#define AO_SUBCTRL_WDOG5_CLK_SEL_LEN    1
#define AO_SUBCTRL_WDOG5_CLK_SEL_OFFSET 0

#define AO_SUBCTRL_ICG_EN_SMMU_TCU_LEN    1
#define AO_SUBCTRL_ICG_EN_SMMU_TCU_OFFSET 1
#define AO_SUBCTRL_ICG_EN_SMMU_TBU_LEN    1
#define AO_SUBCTRL_ICG_EN_SMMU_TBU_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_SMMU_TCU_LEN    1
#define AO_SUBCTRL_ICG_DIS_SMMU_TCU_OFFSET 1
#define AO_SUBCTRL_ICG_DIS_SMMU_TBU_LEN    1
#define AO_SUBCTRL_ICG_DIS_SMMU_TBU_OFFSET 0

#define AO_SUBCTRL_ICG_EN_I2C4_LEN    1
#define AO_SUBCTRL_ICG_EN_I2C4_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_I2C4_LEN    1
#define AO_SUBCTRL_ICG_DIS_I2C4_OFFSET 0

#define AO_SUBCTRL_ICG_EN_I2C5_LEN    1
#define AO_SUBCTRL_ICG_EN_I2C5_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_I2C5_LEN    1
#define AO_SUBCTRL_ICG_DIS_I2C5_OFFSET 0

#define AO_SUBCTRL_ICG_EN_I2C6_LEN    1
#define AO_SUBCTRL_ICG_EN_I2C6_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_I2C6_LEN    1
#define AO_SUBCTRL_ICG_DIS_I2C6_OFFSET 0

#define AO_SUBCTRL_ICG_EN_I2C9_LEN    1
#define AO_SUBCTRL_ICG_EN_I2C9_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_I2C9_LEN    1
#define AO_SUBCTRL_ICG_DIS_I2C9_OFFSET 0

#define AO_SUBCTRL_ICG_EN_SPI_LEN    1
#define AO_SUBCTRL_ICG_EN_SPI_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_SPI_LEN    1
#define AO_SUBCTRL_ICG_DIS_SPI_OFFSET 0

#define AO_SUBCTRL_ICG_EN_SMBUS_LEN    1
#define AO_SUBCTRL_ICG_EN_SMBUS_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_SMBUS_LEN    1
#define AO_SUBCTRL_ICG_DIS_SMBUS_OFFSET 0

#define AO_SUBCTRL_ICG_EN_GPIO_DB_LEN    1
#define AO_SUBCTRL_ICG_EN_GPIO_DB_OFFSET 2
#define AO_SUBCTRL_ICG_EN_GPIO_LEN       2
#define AO_SUBCTRL_ICG_EN_GPIO_OFFSET    0

#define AO_SUBCTRL_ICG_DIS_GPIO_DB_LEN    1
#define AO_SUBCTRL_ICG_DIS_GPIO_DB_OFFSET 2
#define AO_SUBCTRL_ICG_DIS_GPIO_LEN       2
#define AO_SUBCTRL_ICG_DIS_GPIO_OFFSET    0

#define AO_SUBCTRL_ICG_EN_UART_LEN    1
#define AO_SUBCTRL_ICG_EN_UART_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_UART_LEN    1
#define AO_SUBCTRL_ICG_DIS_UART_OFFSET 0

#define AO_SUBCTRL_ICG_EN_GPIO8_DB_LEN    1
#define AO_SUBCTRL_ICG_EN_GPIO8_DB_OFFSET 1
#define AO_SUBCTRL_ICG_EN_GPIO8_LEN       1
#define AO_SUBCTRL_ICG_EN_GPIO8_OFFSET    0

#define AO_SUBCTRL_ICG_DIS_GPIO8_DB_LEN    1
#define AO_SUBCTRL_ICG_DIS_GPIO8_DB_OFFSET 1
#define AO_SUBCTRL_ICG_DIS_GPIO8_LEN       1
#define AO_SUBCTRL_ICG_DIS_GPIO8_OFFSET    0

#define AO_SUBCTRL_ICG_EN_SYSCNT_LEN    1
#define AO_SUBCTRL_ICG_EN_SYSCNT_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_SYSCNT_LEN    1
#define AO_SUBCTRL_ICG_DIS_SYSCNT_OFFSET 0

#define AO_SUBCTRL_ICG_EN_PMBUS0_LEN    1
#define AO_SUBCTRL_ICG_EN_PMBUS0_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_PMBUS0_LEN    1
#define AO_SUBCTRL_ICG_DIS_PMBUS0_OFFSET 0

#define AO_SUBCTRL_ICG_EN_PMBUS1_LEN    1
#define AO_SUBCTRL_ICG_EN_PMBUS1_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_PMBUS1_LEN    1
#define AO_SUBCTRL_ICG_DIS_PMBUS1_OFFSET 0

#define AO_SUBCTRL_ICG_EN_PMCTRL_LEN    1
#define AO_SUBCTRL_ICG_EN_PMCTRL_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_PMCTRL_LEN    1
#define AO_SUBCTRL_ICG_DIS_PMCTRL_OFFSET 0

#define AO_SUBCTRL_ICG_EN_PMPWM_LEN    1
#define AO_SUBCTRL_ICG_EN_PMPWM_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_PMPWM_LEN    1
#define AO_SUBCTRL_ICG_DIS_PMPWM_OFFSET 0

#define AO_SUBCTRL_ICG_EN_8K_LEN    1
#define AO_SUBCTRL_ICG_EN_8K_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_8K_LEN    1
#define AO_SUBCTRL_ICG_DIS_8K_OFFSET 0

#define AO_SUBCTRL_ICG_EN_WDOG0_LEN    1
#define AO_SUBCTRL_ICG_EN_WDOG0_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_WDOG0_LEN    1
#define AO_SUBCTRL_ICG_DIS_WDOG0_OFFSET 0

#define AO_SUBCTRL_ICG_EN_WDOG1_LEN    1
#define AO_SUBCTRL_ICG_EN_WDOG1_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_WDOG1_LEN    1
#define AO_SUBCTRL_ICG_DIS_WDOG1_OFFSET 0

#define AO_SUBCTRL_ICG_EN_WDOG2_LEN    1
#define AO_SUBCTRL_ICG_EN_WDOG2_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_WDOG2_LEN    1
#define AO_SUBCTRL_ICG_DIS_WDOG2_OFFSET 0

#define AO_SUBCTRL_ICG_EN_WDOG3_LEN    1
#define AO_SUBCTRL_ICG_EN_WDOG3_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_WDOG3_LEN    1
#define AO_SUBCTRL_ICG_DIS_WDOG3_OFFSET 0

#define AO_SUBCTRL_ICG_EN_WDOG4_LEN    1
#define AO_SUBCTRL_ICG_EN_WDOG4_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_WDOG4_LEN    1
#define AO_SUBCTRL_ICG_DIS_WDOG4_OFFSET 0

#define AO_SUBCTRL_ICG_EN_WDOG5_LEN    1
#define AO_SUBCTRL_ICG_EN_WDOG5_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_WDOG5_LEN    1
#define AO_SUBCTRL_ICG_DIS_WDOG5_OFFSET 0

#define AO_SUBCTRL_ICG_EN_TIMER0_LEN    1
#define AO_SUBCTRL_ICG_EN_TIMER0_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_TIMER0_LEN    1
#define AO_SUBCTRL_ICG_DIS_TIMER0_OFFSET 0

#define AO_SUBCTRL_ICG_EN_TIMER1_LEN    1
#define AO_SUBCTRL_ICG_EN_TIMER1_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_TIMER1_LEN    1
#define AO_SUBCTRL_ICG_DIS_TIMER1_OFFSET 0

#define AO_SUBCTRL_ICG_EN_GICD_LEN    1
#define AO_SUBCTRL_ICG_EN_GICD_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_GICD_LEN    1
#define AO_SUBCTRL_ICG_DIS_GICD_OFFSET 0

#define AO_SUBCTRL_ICG_EN_ITS_LEN    1
#define AO_SUBCTRL_ICG_EN_ITS_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_ITS_LEN    1
#define AO_SUBCTRL_ICG_DIS_ITS_OFFSET 0

#define AO_SUBCTRL_ICG_EN_APB_MBIGEN_LEN    1
#define AO_SUBCTRL_ICG_EN_APB_MBIGEN_OFFSET 1
#define AO_SUBCTRL_ICG_EN_MBIGEN_LEN        1
#define AO_SUBCTRL_ICG_EN_MBIGEN_OFFSET     0

#define AO_SUBCTRL_ICG_DIS_APB_MBIGEN_LEN    1
#define AO_SUBCTRL_ICG_DIS_APB_MBIGEN_OFFSET 1
#define AO_SUBCTRL_ICG_DIS_MBIGEN_LEN        1
#define AO_SUBCTRL_ICG_DIS_MBIGEN_OFFSET     0

#define AO_SUBCTRL_ICG_EN_LP_TIMER1_LEN    1
#define AO_SUBCTRL_ICG_EN_LP_TIMER1_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_LP_TIMER1_LEN    1
#define AO_SUBCTRL_ICG_DIS_LP_TIMER1_OFFSET 0

#define AO_SUBCTRL_ICG_EN_LP_TIMER2_LEN    1
#define AO_SUBCTRL_ICG_EN_LP_TIMER2_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_LP_TIMER2_LEN    1
#define AO_SUBCTRL_ICG_DIS_LP_TIMER2_OFFSET 0

#define AO_SUBCTRL_ICG_EN_LP_TIMER3_LEN    1
#define AO_SUBCTRL_ICG_EN_LP_TIMER3_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_LP_TIMER3_LEN    1
#define AO_SUBCTRL_ICG_DIS_LP_TIMER3_OFFSET 0

#define AO_SUBCTRL_ICG_EN_OS_TIMER_LEN    2
#define AO_SUBCTRL_ICG_EN_OS_TIMER_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_OS_TIMER_LEN    2
#define AO_SUBCTRL_ICG_DIS_OS_TIMER_OFFSET 0

#define AO_SUBCTRL_ICG_EN_LP_WDOG_LEN    1
#define AO_SUBCTRL_ICG_EN_LP_WDOG_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_LP_WDOG_LEN    1
#define AO_SUBCTRL_ICG_DIS_LP_WDOG_OFFSET 0

#define AO_SUBCTRL_ICG_EN_IPC_S_LEN    1
#define AO_SUBCTRL_ICG_EN_IPC_S_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_IPC_S_LEN    1
#define AO_SUBCTRL_ICG_DIS_IPC_S_OFFSET 0

#define AO_SUBCTRL_ICG_EN_IPC_NS_LEN    1
#define AO_SUBCTRL_ICG_EN_IPC_NS_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_IPC_NS_LEN    1
#define AO_SUBCTRL_ICG_DIS_IPC_NS_OFFSET 0

#define AO_SUBCTRL_ICG_EN_TRNG_HPRE_LEN    1
#define AO_SUBCTRL_ICG_EN_TRNG_HPRE_OFFSET 1
#define AO_SUBCTRL_ICG_EN_TRNG_LEN         1
#define AO_SUBCTRL_ICG_EN_TRNG_OFFSET      0

#define AO_SUBCTRL_ICG_DIS_TRNG_HPRE_LEN    1
#define AO_SUBCTRL_ICG_DIS_TRNG_HPRE_OFFSET 1
#define AO_SUBCTRL_ICG_DIS_TRNG_LEN         1
#define AO_SUBCTRL_ICG_DIS_TRNG_OFFSET      0

#define AO_SUBCTRL_ICG_EN_TIMER2_LEN    1
#define AO_SUBCTRL_ICG_EN_TIMER2_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_TIMER2_LEN    1
#define AO_SUBCTRL_ICG_DIS_TIMER2_OFFSET 0

#define AO_SUBCTRL_ICG_EN_TIMER3_LEN    1
#define AO_SUBCTRL_ICG_EN_TIMER3_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_TIMER3_LEN    1
#define AO_SUBCTRL_ICG_DIS_TIMER3_OFFSET 0

#define AO_SUBCTRL_ICG_EN_LP_TIMER0_LEN    1
#define AO_SUBCTRL_ICG_EN_LP_TIMER0_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_LP_TIMER0_LEN    1
#define AO_SUBCTRL_ICG_DIS_LP_TIMER0_OFFSET 0

#define AO_SUBCTRL_ICG_EN_LSADC_CS_LEN    1
#define AO_SUBCTRL_ICG_EN_LSADC_CS_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_LSADC_CS_LEN    1
#define AO_SUBCTRL_ICG_DIS_LSADC_CS_OFFSET 0

#define AO_SUBCTRL_ICG_EN_PAD_DB_LEN    1
#define AO_SUBCTRL_ICG_EN_PAD_DB_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_PAD_DB_LEN    1
#define AO_SUBCTRL_ICG_DIS_PAD_DB_OFFSET 0

#define AO_SUBCTRL_ICG_EN_DJTAG_LEN    1
#define AO_SUBCTRL_ICG_EN_DJTAG_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_DJTAG_LEN    1
#define AO_SUBCTRL_ICG_DIS_DJTAG_OFFSET 0

#define AO_SUBCTRL_ICG_EN_FUNC_MBIST_LEN    1
#define AO_SUBCTRL_ICG_EN_FUNC_MBIST_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_FUNC_MBIST_LEN    1
#define AO_SUBCTRL_ICG_DIS_FUNC_MBIST_OFFSET 0

#define AO_SUBCTRL_ICG_EN_PROBE_LEN    1
#define AO_SUBCTRL_ICG_EN_PROBE_OFFSET 0

#define AO_SUBCTRL_ICG_DIS_PROBE_LEN    1
#define AO_SUBCTRL_ICG_DIS_PROBE_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_ITS_LEN    1
#define AO_SUBCTRL_SRST_REQ_ITS_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_ITS_LEN    1
#define AO_SUBCTRL_SRST_DREQ_ITS_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_MBIGEN_LEN    1
#define AO_SUBCTRL_SRST_REQ_MBIGEN_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_MBIGEN_LEN    1
#define AO_SUBCTRL_SRST_DREQ_MBIGEN_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_GICD_LEN    1
#define AO_SUBCTRL_SRST_REQ_GICD_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_GICD_LEN    1
#define AO_SUBCTRL_SRST_DREQ_GICD_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_I2C4_LEN    1
#define AO_SUBCTRL_SRST_REQ_I2C4_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_I2C4_LEN    1
#define AO_SUBCTRL_SRST_DREQ_I2C4_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_I2C5_LEN    1
#define AO_SUBCTRL_SRST_REQ_I2C5_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_I2C5_LEN    1
#define AO_SUBCTRL_SRST_DREQ_I2C5_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_I2C6_LEN    1
#define AO_SUBCTRL_SRST_REQ_I2C6_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_I2C6_LEN    1
#define AO_SUBCTRL_SRST_DREQ_I2C6_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_I2C9_LEN    1
#define AO_SUBCTRL_SRST_REQ_I2C9_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_I2C9_LEN    1
#define AO_SUBCTRL_SRST_DREQ_I2C9_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_SPI_LEN    1
#define AO_SUBCTRL_SRST_REQ_SPI_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_SPI_LEN    1
#define AO_SUBCTRL_SRST_DREQ_SPI_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_SMBUS_LEN    1
#define AO_SUBCTRL_SRST_REQ_SMBUS_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_SMBUS_LEN    1
#define AO_SUBCTRL_SRST_DREQ_SMBUS_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_GPIO_DB_LEN    1
#define AO_SUBCTRL_SRST_REQ_GPIO_DB_OFFSET 2
#define AO_SUBCTRL_SRST_REQ_GPIO_LEN       2
#define AO_SUBCTRL_SRST_REQ_GPIO_OFFSET    0

#define AO_SUBCTRL_SRST_DREQ_GPIO_DB_LEN    1
#define AO_SUBCTRL_SRST_DREQ_GPIO_DB_OFFSET 2
#define AO_SUBCTRL_SRST_DREQ_GPIO_LEN       2
#define AO_SUBCTRL_SRST_DREQ_GPIO_OFFSET    0

#define AO_SUBCTRL_SRST_REQ_UART_LEN    1
#define AO_SUBCTRL_SRST_REQ_UART_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_UART_LEN    1
#define AO_SUBCTRL_SRST_DREQ_UART_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_GPIO8_DB_LEN    1
#define AO_SUBCTRL_SRST_REQ_GPIO8_DB_OFFSET 1
#define AO_SUBCTRL_SRST_REQ_GPIO8_LEN       1
#define AO_SUBCTRL_SRST_REQ_GPIO8_OFFSET    0

#define AO_SUBCTRL_SRST_DREQ_GPIO8_DB_LEN    1
#define AO_SUBCTRL_SRST_DREQ_GPIO8_DB_OFFSET 1
#define AO_SUBCTRL_SRST_DREQ_GPIO8_LEN       1
#define AO_SUBCTRL_SRST_DREQ_GPIO8_OFFSET    0

#define AO_SUBCTRL_SRST_REQ_APB_SUBCTRL_LEN    1
#define AO_SUBCTRL_SRST_REQ_APB_SUBCTRL_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_APB_SUBCTRL_LEN    1
#define AO_SUBCTRL_SRST_DREQ_APB_SUBCTRL_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_SYSCNT_LEN    1
#define AO_SUBCTRL_SRST_REQ_SYSCNT_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_SYSCNT_LEN    1
#define AO_SUBCTRL_SRST_DREQ_SYSCNT_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_PMCTRL_LEN    1
#define AO_SUBCTRL_SRST_REQ_PMCTRL_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_PMCTRL_LEN    1
#define AO_SUBCTRL_SRST_DREQ_PMCTRL_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_PMBUS0_LEN    1
#define AO_SUBCTRL_SRST_REQ_PMBUS0_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_PMBUS0_LEN    1
#define AO_SUBCTRL_SRST_DREQ_PMBUS0_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_PMBUS1_LEN    1
#define AO_SUBCTRL_SRST_REQ_PMBUS1_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_PMBUS1_LEN    1
#define AO_SUBCTRL_SRST_DREQ_PMBUS1_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_PMPWM_LEN    1
#define AO_SUBCTRL_SRST_REQ_PMPWM_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_PMPWM_LEN    1
#define AO_SUBCTRL_SRST_DREQ_PMPWM_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_8K_LEN    1
#define AO_SUBCTRL_SRST_REQ_8K_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_8K_LEN    1
#define AO_SUBCTRL_SRST_DREQ_8K_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_WDOG0_LEN    1
#define AO_SUBCTRL_SRST_REQ_WDOG0_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_WDOG0_LEN    1
#define AO_SUBCTRL_SRST_DREQ_WDOG0_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_WDOG1_LEN    1
#define AO_SUBCTRL_SRST_REQ_WDOG1_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_WDOG1_LEN    1
#define AO_SUBCTRL_SRST_DREQ_WDOG1_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_WDOG2_LEN    1
#define AO_SUBCTRL_SRST_REQ_WDOG2_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_WDOG2_LEN    1
#define AO_SUBCTRL_SRST_DREQ_WDOG2_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_WDOG3_LEN    1
#define AO_SUBCTRL_SRST_REQ_WDOG3_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_WDOG3_LEN    1
#define AO_SUBCTRL_SRST_DREQ_WDOG3_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_WDOG4_LEN    1
#define AO_SUBCTRL_SRST_REQ_WDOG4_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_WDOG4_LEN    1
#define AO_SUBCTRL_SRST_DREQ_WDOG4_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_WDOG5_LEN    1
#define AO_SUBCTRL_SRST_REQ_WDOG5_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_WDOG5_LEN    1
#define AO_SUBCTRL_SRST_DREQ_WDOG5_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_TIMER0_LEN    1
#define AO_SUBCTRL_SRST_REQ_TIMER0_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_TIMER0_LEN    1
#define AO_SUBCTRL_SRST_DREQ_TIMER0_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_TIMER1_LEN    1
#define AO_SUBCTRL_SRST_REQ_TIMER1_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_TIMER1_LEN    1
#define AO_SUBCTRL_SRST_DREQ_TIMER1_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_TIMER2_LEN    1
#define AO_SUBCTRL_SRST_REQ_TIMER2_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_TIMER2_LEN    1
#define AO_SUBCTRL_SRST_DREQ_TIMER2_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_TIMER3_LEN    1
#define AO_SUBCTRL_SRST_REQ_TIMER3_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_TIMER3_LEN    1
#define AO_SUBCTRL_SRST_DREQ_TIMER3_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_LP_TIMER0_LEN    1
#define AO_SUBCTRL_SRST_REQ_LP_TIMER0_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_LP_TIMER0_LEN    1
#define AO_SUBCTRL_SRST_DREQ_LP_TIMER0_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_LP_TIMER1_LEN    1
#define AO_SUBCTRL_SRST_REQ_LP_TIMER1_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_LP_TIMER1_LEN    1
#define AO_SUBCTRL_SRST_DREQ_LP_TIMER1_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_LP_TIMER2_LEN    1
#define AO_SUBCTRL_SRST_REQ_LP_TIMER2_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_LP_TIMER2_LEN    1
#define AO_SUBCTRL_SRST_DREQ_LP_TIMER2_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_LP_TIMER3_LEN    1
#define AO_SUBCTRL_SRST_REQ_LP_TIMER3_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_LP_TIMER3_LEN    1
#define AO_SUBCTRL_SRST_DREQ_LP_TIMER3_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_OS_TIMER_LEN    2
#define AO_SUBCTRL_SRST_REQ_OS_TIMER_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_OS_TIMER_LEN    2
#define AO_SUBCTRL_SRST_DREQ_OS_TIMER_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_LP_WDOG_LEN    1
#define AO_SUBCTRL_SRST_REQ_LP_WDOG_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_LP_WDOG_LEN    1
#define AO_SUBCTRL_SRST_DREQ_LP_WDOG_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_IPC_S_LEN    1
#define AO_SUBCTRL_SRST_REQ_IPC_S_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_IPC_S_LEN    1
#define AO_SUBCTRL_SRST_DREQ_IPC_S_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_IPC_NS_LEN    1
#define AO_SUBCTRL_SRST_REQ_IPC_NS_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_IPC_NS_LEN    1
#define AO_SUBCTRL_SRST_DREQ_IPC_NS_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_TRNG_HPRE_LEN    1
#define AO_SUBCTRL_SRST_REQ_TRNG_HPRE_OFFSET 1
#define AO_SUBCTRL_SRST_REQ_TRNG_LEN         1
#define AO_SUBCTRL_SRST_REQ_TRNG_OFFSET      0

#define AO_SUBCTRL_SRST_DREQ_TRNG_HPRE_LEN    1
#define AO_SUBCTRL_SRST_DREQ_TRNG_HPRE_OFFSET 1
#define AO_SUBCTRL_SRST_DREQ_TRNG_LEN         1
#define AO_SUBCTRL_SRST_DREQ_TRNG_OFFSET      0

#define AO_SUBCTRL_SRST_REQ_BISR_S_POWER_LEN    1
#define AO_SUBCTRL_SRST_REQ_BISR_S_POWER_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_BISR_S_POWER_LEN    1
#define AO_SUBCTRL_SRST_DREQ_BISR_S_POWER_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_PAD_DB_LEN    1
#define AO_SUBCTRL_SRST_REQ_PAD_DB_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_PAD_DB_LEN    1
#define AO_SUBCTRL_SRST_DREQ_PAD_DB_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_DJTAG_LEN    1
#define AO_SUBCTRL_SRST_REQ_DJTAG_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_DJTAG_LEN    1
#define AO_SUBCTRL_SRST_DREQ_DJTAG_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_FUNC_MBIST_LEN    1
#define AO_SUBCTRL_SRST_REQ_FUNC_MBIST_OFFSET 0

#define AO_SUBCTRL_SRST_DREQ_FUNC_MBIST_LEN    1
#define AO_SUBCTRL_SRST_DREQ_FUNC_MBIST_OFFSET 0

#define AO_SUBCTRL_SRST_REQ_LSADC_REG7_LEN    1
#define AO_SUBCTRL_SRST_REQ_LSADC_REG7_OFFSET 1
#define AO_SUBCTRL_SRST_REQ_LSADC_PD_LEN      1
#define AO_SUBCTRL_SRST_REQ_LSADC_PD_OFFSET   0

#define AO_SUBCTRL_SRST_DREQ_LSADC_REG7_LEN    1
#define AO_SUBCTRL_SRST_DREQ_LSADC_REG7_OFFSET 1
#define AO_SUBCTRL_SRST_DREQ_LSADC_PD_LEN      1
#define AO_SUBCTRL_SRST_DREQ_LSADC_PD_OFFSET   0

#define AO_SUBCTRL_CHAIN_ERR_INT_LEN    1
#define AO_SUBCTRL_CHAIN_ERR_INT_OFFSET 0

#define AO_SUBCTRL_CHAIN_ERR_INTMASK_LEN    1
#define AO_SUBCTRL_CHAIN_ERR_INTMASK_OFFSET 0

#define AO_SUBCTRL_CHAIN_ERR_INTSTATUS_LEN    1
#define AO_SUBCTRL_CHAIN_ERR_INTSTATUS_OFFSET 0

#define AO_SUBCTRL_DISPATCH_ERRRSP_LEN    1
#define AO_SUBCTRL_DISPATCH_ERRRSP_OFFSET 0

#define AO_SUBCTRL_GPIO1_SYN_EN_LEN    1
#define AO_SUBCTRL_GPIO1_SYN_EN_OFFSET 1
#define AO_SUBCTRL_GPIO0_SYN_EN_LEN    1
#define AO_SUBCTRL_GPIO0_SYN_EN_OFFSET 0

#define AO_SUBCTRL_GPIO8_SYN_EN_LEN    1
#define AO_SUBCTRL_GPIO8_SYN_EN_OFFSET 0

#define AO_SUBCTRL_GIC_NOCMT_IRQ_LAT_LEN    4
#define AO_SUBCTRL_GIC_NOCMT_IRQ_LAT_OFFSET 0

#define AO_SUBCTRL_GIC_NOCMT_IRQ_MASK_LEN    4
#define AO_SUBCTRL_GIC_NOCMT_IRQ_MASK_OFFSET 0

#define AO_SUBCTRL_GIC_NOCMT_IRQ_STATUS_LEN    4
#define AO_SUBCTRL_GIC_NOCMT_IRQ_STATUS_OFFSET 0

#define AO_SUBCTRL_GIC_NOCMT_RST_OUT_EN_LEN    1
#define AO_SUBCTRL_GIC_NOCMT_RST_OUT_EN_OFFSET 0

#define AO_SUBCTRL_GIC_NOCMT_IRQ_SEL_LEN    1
#define AO_SUBCTRL_GIC_NOCMT_IRQ_SEL_OFFSET 0

#define AO_SUBCTRL_USB_NFE_PULSE_WID_LEN    6
#define AO_SUBCTRL_USB_NFE_PULSE_WID_OFFSET 0

#define AO_SUBCTRL_CMD_DELY_DEFINE_LEN    32
#define AO_SUBCTRL_CMD_DELY_DEFINE_OFFSET 0

#define AO_SUBCTRL_TP_RAM_TMOD_LEN    32
#define AO_SUBCTRL_TP_RAM_TMOD_OFFSET 0

#define AO_SUBCTRL_SP_RAM_TMOD_LEN    32
#define AO_SUBCTRL_SP_RAM_TMOD_OFFSET 0

#define AO_SUBCTRL_MEM_POWER_MODE_LEN    4
#define AO_SUBCTRL_MEM_POWER_MODE_OFFSET 0

#define AO_SUBCTRL_ASYNC_FIFO_EMPTY_CLAMP_LEN    1
#define AO_SUBCTRL_ASYNC_FIFO_EMPTY_CLAMP_OFFSET 0

#define AO_SUBCTRL_BUS_NUM_LEN    8
#define AO_SUBCTRL_BUS_NUM_OFFSET 0

#define AO_SUBCTRL_RD_WAIT_CYCLE_LEN    32
#define AO_SUBCTRL_RD_WAIT_CYCLE_OFFSET 0

#define AO_SUBCTRL_SUBSYS_FORCE_BUSY_LEN    1
#define AO_SUBCTRL_SUBSYS_FORCE_BUSY_OFFSET 31
#define AO_SUBCTRL_MODULE_FORCE_BUSY_LEN    16
#define AO_SUBCTRL_MODULE_FORCE_BUSY_OFFSET 0

#define AO_SUBCTRL_MODULE_FORCE_IDLE_LEN    16
#define AO_SUBCTRL_MODULE_FORCE_IDLE_OFFSET 0

#define AO_SUBCTRL_AUTOLF_IDLE_CLK_CYCLE_TH_LEN    16
#define AO_SUBCTRL_AUTOLF_IDLE_CLK_CYCLE_TH_OFFSET 0

#define AO_SUBCTRL_AUTOLF_IDLE_CNT_CLR_LEN        1
#define AO_SUBCTRL_AUTOLF_IDLE_CNT_CLR_OFFSET     1
#define AO_SUBCTRL_AUTOLF_FORCE_CFG_ENABLE_LEN    1
#define AO_SUBCTRL_AUTOLF_FORCE_CFG_ENABLE_OFFSET 0

#define AO_SUBCTRL_IDLE_SUBSYS_STATUS_LEN    1
#define AO_SUBCTRL_IDLE_SUBSYS_STATUS_OFFSET 31
#define AO_SUBCTRL_IDLE_STATUS_LEN           16
#define AO_SUBCTRL_IDLE_STATUS_OFFSET        0

#define AO_SUBCTRL_IDLE_CNT_LEN    32
#define AO_SUBCTRL_IDLE_CNT_OFFSET 0

#define AO_SUBCTRL_SUBSYS_FORCE_BUSY_L2_LEN    1
#define AO_SUBCTRL_SUBSYS_FORCE_BUSY_L2_OFFSET 31
#define AO_SUBCTRL_MODULE_FORCE_BUSY_L2_LEN    16
#define AO_SUBCTRL_MODULE_FORCE_BUSY_L2_OFFSET 0

#define AO_SUBCTRL_MODULE_FORCE_IDLE_L2_LEN    16
#define AO_SUBCTRL_MODULE_FORCE_IDLE_L2_OFFSET 0

#define AO_SUBCTRL_AUTOLF_IDLE_CLK_CYCLE_TH_L2_LEN    16
#define AO_SUBCTRL_AUTOLF_IDLE_CLK_CYCLE_TH_L2_OFFSET 0

#define AO_SUBCTRL_AUTOLF_IDLE_CNT_CLR_L2_LEN        1
#define AO_SUBCTRL_AUTOLF_IDLE_CNT_CLR_L2_OFFSET     1
#define AO_SUBCTRL_AUTOLF_FORCE_CFG_ENABLE_L2_LEN    1
#define AO_SUBCTRL_AUTOLF_FORCE_CFG_ENABLE_L2_OFFSET 0

#define AO_SUBCTRL_IDLE_SUBSYS_STATUS_L2_LEN    1
#define AO_SUBCTRL_IDLE_SUBSYS_STATUS_L2_OFFSET 31
#define AO_SUBCTRL_IDLE_STATUS_L2_LEN           16
#define AO_SUBCTRL_IDLE_STATUS_L2_OFFSET        0

#define AO_SUBCTRL_IDLE_CNT_L2_LEN    32
#define AO_SUBCTRL_IDLE_CNT_L2_OFFSET 0

#define AO_SUBCTRL_LP_WDG_RST_OUT_EN_LEN    1
#define AO_SUBCTRL_LP_WDG_RST_OUT_EN_OFFSET 6
#define AO_SUBCTRL_PWR_SEQ_CTRL_LEN         6
#define AO_SUBCTRL_PWR_SEQ_CTRL_OFFSET      0

#define AO_SUBCTRL_PCIE_RST_BYPASS_LEN           1
#define AO_SUBCTRL_PCIE_RST_BYPASS_OFFSET        1
#define AO_SUBCTRL_HOT_RESET_HIPCIEC_MASK_LEN    1
#define AO_SUBCTRL_HOT_RESET_HIPCIEC_MASK_OFFSET 0

#define AO_SUBCTRL_PCIE_PERST_CTRL_OUT_LEN    4
#define AO_SUBCTRL_PCIE_PERST_CTRL_OUT_OFFSET 0

#define AO_SUBCTRL_HISS_CORE_SEC_CTRL_LEN    32
#define AO_SUBCTRL_HISS_CORE_SEC_CTRL_OFFSET 0

#define AO_SUBCTRL_JA_HEART_BEAT_NUM_LEN    32
#define AO_SUBCTRL_JA_HEART_BEAT_NUM_OFFSET 0

#define AO_SUBCTRL_JA_SELFTEST_ENB_LEN    1
#define AO_SUBCTRL_JA_SELFTEST_ENB_OFFSET 2
#define AO_SUBCTRL_JA_EMSA_PSS_SEL_LEN    1
#define AO_SUBCTRL_JA_EMSA_PSS_SEL_OFFSET 1
#define AO_SUBCTRL_JA_LP_EN_LEN           1
#define AO_SUBCTRL_JA_LP_EN_OFFSET        0

#define AO_SUBCTRL_JA_RESULT_31_0_LEN    32
#define AO_SUBCTRL_JA_RESULT_31_0_OFFSET 0

#define AO_SUBCTRL_JA_RESULT_63_32_LEN    32
#define AO_SUBCTRL_JA_RESULT_63_32_OFFSET 0

#define AO_SUBCTRL_JA_RESULT_EN_LEN    1
#define AO_SUBCTRL_JA_RESULT_EN_OFFSET 0

#define AO_SUBCTRL_INT_TOP2HISS_MASK_0_LEN    32
#define AO_SUBCTRL_INT_TOP2HISS_MASK_0_OFFSET 0

#define AO_SUBCTRL_INT_TOP2HISS_MASK_1_LEN    32
#define AO_SUBCTRL_INT_TOP2HISS_MASK_1_OFFSET 0

#define AO_SUBCTRL_INT_LP2HISS_MASK_0_LEN    32
#define AO_SUBCTRL_INT_LP2HISS_MASK_0_OFFSET 0

#define AO_SUBCTRL_INT_LP2HISS_MASK_1_LEN    32
#define AO_SUBCTRL_INT_LP2HISS_MASK_1_OFFSET 0

#define AO_SUBCTRL_INT_LP2HISS_MASK_2_LEN    32
#define AO_SUBCTRL_INT_LP2HISS_MASK_2_OFFSET 0

#define AO_SUBCTRL_INT_LP2HISS_MASK_3_LEN    32
#define AO_SUBCTRL_INT_LP2HISS_MASK_3_OFFSET 0

#define AO_SUBCTRL_INT_LP2HISS_MASK_4_LEN    32
#define AO_SUBCTRL_INT_LP2HISS_MASK_4_OFFSET 0

#define AO_SUBCTRL_INT_LP2HISS_MASK_5_LEN    32
#define AO_SUBCTRL_INT_LP2HISS_MASK_5_OFFSET 0

#define AO_SUBCTRL_INT_LP2HISS_MASK_6_LEN    32
#define AO_SUBCTRL_INT_LP2HISS_MASK_6_OFFSET 0

#define AO_SUBCTRL_INT_LP2HISS_MASK_7_LEN    32
#define AO_SUBCTRL_INT_LP2HISS_MASK_7_OFFSET 0

#define AO_SUBCTRL_PAD_TPM_SRC_INV_LEN    1
#define AO_SUBCTRL_PAD_TPM_SRC_INV_OFFSET 0

#define AO_SUBCTRL_PAD_TPM_N_INT_MASK_GIC_LEN    1
#define AO_SUBCTRL_PAD_TPM_N_INT_MASK_GIC_OFFSET 0

#define AO_SUBCTRL_PAD_TPM_N_INT_MASK_HISS_LEN    1
#define AO_SUBCTRL_PAD_TPM_N_INT_MASK_HISS_OFFSET 0

#define AO_SUBCTRL_OS_TIMER_CLK_SEL1_LEN    2
#define AO_SUBCTRL_OS_TIMER_CLK_SEL1_OFFSET 2
#define AO_SUBCTRL_OS_TIMER_CLK_SEL0_LEN    2
#define AO_SUBCTRL_OS_TIMER_CLK_SEL0_OFFSET 0

#define AO_SUBCTRL_TIMER0_CLK_SEL1_LEN    1
#define AO_SUBCTRL_TIMER0_CLK_SEL1_OFFSET 1
#define AO_SUBCTRL_TIMER0_CLK_SEL0_LEN    1
#define AO_SUBCTRL_TIMER0_CLK_SEL0_OFFSET 0

#define AO_SUBCTRL_TIMER1_CLK_SEL1_LEN    1
#define AO_SUBCTRL_TIMER1_CLK_SEL1_OFFSET 1
#define AO_SUBCTRL_TIMER1_CLK_SEL0_LEN    1
#define AO_SUBCTRL_TIMER1_CLK_SEL0_OFFSET 0

#define AO_SUBCTRL_TIMER2_CLK_SEL1_LEN    1
#define AO_SUBCTRL_TIMER2_CLK_SEL1_OFFSET 1
#define AO_SUBCTRL_TIMER2_CLK_SEL0_LEN    1
#define AO_SUBCTRL_TIMER2_CLK_SEL0_OFFSET 0

#define AO_SUBCTRL_TIMER3_CLK_SEL1_LEN    1
#define AO_SUBCTRL_TIMER3_CLK_SEL1_OFFSET 1
#define AO_SUBCTRL_TIMER3_CLK_SEL0_LEN    1
#define AO_SUBCTRL_TIMER3_CLK_SEL0_OFFSET 0

#define AO_SUBCTRL_LP_TIMER0_CLK_SEL1_LEN    1
#define AO_SUBCTRL_LP_TIMER0_CLK_SEL1_OFFSET 1
#define AO_SUBCTRL_LP_TIMER0_CLK_SEL0_LEN    1
#define AO_SUBCTRL_LP_TIMER0_CLK_SEL0_OFFSET 0

#define AO_SUBCTRL_LP_TIMER1_CLK_SEL1_LEN    1
#define AO_SUBCTRL_LP_TIMER1_CLK_SEL1_OFFSET 1
#define AO_SUBCTRL_LP_TIMER1_CLK_SEL0_LEN    1
#define AO_SUBCTRL_LP_TIMER1_CLK_SEL0_OFFSET 0

#define AO_SUBCTRL_LP_TIMER2_CLK_SEL1_LEN    1
#define AO_SUBCTRL_LP_TIMER2_CLK_SEL1_OFFSET 1
#define AO_SUBCTRL_LP_TIMER2_CLK_SEL0_LEN    1
#define AO_SUBCTRL_LP_TIMER2_CLK_SEL0_OFFSET 0

#define AO_SUBCTRL_LP_TIMER3_CLK_SEL1_LEN    1
#define AO_SUBCTRL_LP_TIMER3_CLK_SEL1_OFFSET 1
#define AO_SUBCTRL_LP_TIMER3_CLK_SEL0_LEN    1
#define AO_SUBCTRL_LP_TIMER3_CLK_SEL0_OFFSET 0

#define AO_SUBCTRL_OS_TIMER_EN_EXTERNAL_LEN    2
#define AO_SUBCTRL_OS_TIMER_EN_EXTERNAL_OFFSET 0

#define AO_SUBCTRL_TIMER0_EN_EXTERNAL_LEN    1
#define AO_SUBCTRL_TIMER0_EN_EXTERNAL_OFFSET 0

#define AO_SUBCTRL_TIMER1_EN_EXTERNAL_LEN    1
#define AO_SUBCTRL_TIMER1_EN_EXTERNAL_OFFSET 0

#define AO_SUBCTRL_TIMER2_EN_EXTERNAL_LEN    1
#define AO_SUBCTRL_TIMER2_EN_EXTERNAL_OFFSET 0

#define AO_SUBCTRL_TIMER3_EN_EXTERNAL_LEN    1
#define AO_SUBCTRL_TIMER3_EN_EXTERNAL_OFFSET 0

#define AO_SUBCTRL_LP_TIMER0_EN_EXTERNAL_LEN    1
#define AO_SUBCTRL_LP_TIMER0_EN_EXTERNAL_OFFSET 0

#define AO_SUBCTRL_LP_TIMER1_EN_EXTERNAL_LEN    1
#define AO_SUBCTRL_LP_TIMER1_EN_EXTERNAL_OFFSET 0

#define AO_SUBCTRL_LP_TIMER2_EN_EXTERNAL_LEN    1
#define AO_SUBCTRL_LP_TIMER2_EN_EXTERNAL_OFFSET 0

#define AO_SUBCTRL_LP_TIMER3_EN_EXTERNAL_LEN    1
#define AO_SUBCTRL_LP_TIMER3_EN_EXTERNAL_OFFSET 0

#define AO_SUBCTRL_DAW_ADDR_SFC_MEM_LEN    20
#define AO_SUBCTRL_DAW_ADDR_SFC_MEM_OFFSET 0

#define AO_SUBCTRL_DAW_SIZE_SFC_MEM_LEN    5
#define AO_SUBCTRL_DAW_SIZE_SFC_MEM_OFFSET 16
#define AO_SUBCTRL_DAW_EN_SFC_MEM_LEN      1
#define AO_SUBCTRL_DAW_EN_SFC_MEM_OFFSET   8

#define AO_SUBCTRL_LSADC0_REG_LEN        4
#define AO_SUBCTRL_LSADC0_REG_OFFSET     24
#define AO_SUBCTRL_LSADC0_SARREG2_LEN    8
#define AO_SUBCTRL_LSADC0_SARREG2_OFFSET 16
#define AO_SUBCTRL_LSADC0_SARREG1_LEN    8
#define AO_SUBCTRL_LSADC0_SARREG1_OFFSET 8
#define AO_SUBCTRL_LSADC0_SARREG0_LEN    7
#define AO_SUBCTRL_LSADC0_SARREG0_OFFSET 0

#define AO_SUBCTRL_LSADC1_REG_LEN        4
#define AO_SUBCTRL_LSADC1_REG_OFFSET     24
#define AO_SUBCTRL_LSADC1_SARREG2_LEN    8
#define AO_SUBCTRL_LSADC1_SARREG2_OFFSET 16
#define AO_SUBCTRL_LSADC1_SARREG1_LEN    8
#define AO_SUBCTRL_LSADC1_SARREG1_OFFSET 8
#define AO_SUBCTRL_LSADC1_SARREG0_LEN    7
#define AO_SUBCTRL_LSADC1_SARREG0_OFFSET 0

#define AO_SUBCTRL_SDS0_DS_LVCCLDO_PWRDNB_DVDDH8_LEN    4
#define AO_SUBCTRL_SDS0_DS_LVCCLDO_PWRDNB_DVDDH8_OFFSET 5
#define AO_SUBCTRL_SDS0_DDS_ISO_ENB_DVDDH8_LEN          2
#define AO_SUBCTRL_SDS0_DDS_ISO_ENB_DVDDH8_OFFSET       3
#define AO_SUBCTRL_SDS0_CS_ISO_ENB_DVDDH8_LEN           2
#define AO_SUBCTRL_SDS0_CS_ISO_ENB_DVDDH8_OFFSET        1
#define AO_SUBCTRL_SDS0_LVR_ENB_DVDDH8_LEN              1
#define AO_SUBCTRL_SDS0_LVR_ENB_DVDDH8_OFFSET           0

#define AO_SUBCTRL_SDS1_DS_LVCCLDO_PWRDNB_DVDDH8_LEN    4
#define AO_SUBCTRL_SDS1_DS_LVCCLDO_PWRDNB_DVDDH8_OFFSET 5
#define AO_SUBCTRL_SDS1_DDS_ISO_ENB_DVDDH8_LEN          2
#define AO_SUBCTRL_SDS1_DDS_ISO_ENB_DVDDH8_OFFSET       3
#define AO_SUBCTRL_SDS1_CS_ISO_ENB_DVDDH8_LEN           2
#define AO_SUBCTRL_SDS1_CS_ISO_ENB_DVDDH8_OFFSET        1
#define AO_SUBCTRL_SDS1_LVR_ENB_DVDDH8_LEN              1
#define AO_SUBCTRL_SDS1_LVR_ENB_DVDDH8_OFFSET           0

#define AO_SUBCTRL_SDS0_RX_SQDET_VREF_SEL_LEN    12
#define AO_SUBCTRL_SDS0_RX_SQDET_VREF_SEL_OFFSET 8
#define AO_SUBCTRL_SDS0_RX_SQDET_POLARITY_LEN    4
#define AO_SUBCTRL_SDS0_RX_SQDET_POLARITY_OFFSET 4
#define AO_SUBCTRL_SDS0_RX_1K_HIZ_SEL_LEN        4
#define AO_SUBCTRL_SDS0_RX_1K_HIZ_SEL_OFFSET     0

#define AO_SUBCTRL_SDS1_RX_SQDET_VREF_SEL_LEN    12
#define AO_SUBCTRL_SDS1_RX_SQDET_VREF_SEL_OFFSET 8
#define AO_SUBCTRL_SDS1_RX_SQDET_POLARITY_LEN    4
#define AO_SUBCTRL_SDS1_RX_SQDET_POLARITY_OFFSET 4
#define AO_SUBCTRL_SDS1_RX_1K_HIZ_SEL_LEN        4
#define AO_SUBCTRL_SDS1_RX_1K_HIZ_SEL_OFFSET     0

#define AO_SUBCTRL_REPAIR_LOAD_RSTN_LEN    30
#define AO_SUBCTRL_REPAIR_LOAD_RSTN_OFFSET 0

#define AO_SUBCTRL_ICG_ST_SMMU_TCU_LEN    1
#define AO_SUBCTRL_ICG_ST_SMMU_TCU_OFFSET 1
#define AO_SUBCTRL_ICG_ST_SMMU_TBU_LEN    1
#define AO_SUBCTRL_ICG_ST_SMMU_TBU_OFFSET 0

#define AO_SUBCTRL_ICG_ST_I2C4_LEN    1
#define AO_SUBCTRL_ICG_ST_I2C4_OFFSET 0

#define AO_SUBCTRL_ICG_ST_I2C5_LEN    1
#define AO_SUBCTRL_ICG_ST_I2C5_OFFSET 0

#define AO_SUBCTRL_ICG_ST_I2C6_LEN    1
#define AO_SUBCTRL_ICG_ST_I2C6_OFFSET 0

#define AO_SUBCTRL_ICG_ST_I2C9_LEN    1
#define AO_SUBCTRL_ICG_ST_I2C9_OFFSET 0

#define AO_SUBCTRL_ICG_ST_SPI_LEN    1
#define AO_SUBCTRL_ICG_ST_SPI_OFFSET 0

#define AO_SUBCTRL_ICG_ST_SMBUS_LEN    1
#define AO_SUBCTRL_ICG_ST_SMBUS_OFFSET 0

#define AO_SUBCTRL_ICG_ST_GPIO_DB_LEN    1
#define AO_SUBCTRL_ICG_ST_GPIO_DB_OFFSET 2
#define AO_SUBCTRL_ICG_ST_GPIO_LEN       2
#define AO_SUBCTRL_ICG_ST_GPIO_OFFSET    0

#define AO_SUBCTRL_ICG_ST_UART_LEN    1
#define AO_SUBCTRL_ICG_ST_UART_OFFSET 0

#define AO_SUBCTRL_ICG_ST_GPIO8_DB_LEN    1
#define AO_SUBCTRL_ICG_ST_GPIO8_DB_OFFSET 1
#define AO_SUBCTRL_ICG_ST_GPIO8_LEN       1
#define AO_SUBCTRL_ICG_ST_GPIO8_OFFSET    0

#define AO_SUBCTRL_ICG_ST_SYSCNT_LEN    1
#define AO_SUBCTRL_ICG_ST_SYSCNT_OFFSET 0

#define AO_SUBCTRL_ICG_ST_PMBUS0_LEN    1
#define AO_SUBCTRL_ICG_ST_PMBUS0_OFFSET 0

#define AO_SUBCTRL_ICG_ST_PMBUS1_LEN    1
#define AO_SUBCTRL_ICG_ST_PMBUS1_OFFSET 0

#define AO_SUBCTRL_ICG_ST_PMCTRL_LEN    1
#define AO_SUBCTRL_ICG_ST_PMCTRL_OFFSET 0

#define AO_SUBCTRL_ICG_ST_PMPWM_LEN    1
#define AO_SUBCTRL_ICG_ST_PMPWM_OFFSET 0

#define AO_SUBCTRL_ICG_ST_8K_LEN    1
#define AO_SUBCTRL_ICG_ST_8K_OFFSET 0

#define AO_SUBCTRL_ICG_ST_WDOG0_LEN    1
#define AO_SUBCTRL_ICG_ST_WDOG0_OFFSET 0

#define AO_SUBCTRL_ICG_ST_WDOG1_LEN    1
#define AO_SUBCTRL_ICG_ST_WDOG1_OFFSET 0

#define AO_SUBCTRL_ICG_ST_WDOG2_LEN    1
#define AO_SUBCTRL_ICG_ST_WDOG2_OFFSET 0

#define AO_SUBCTRL_ICG_ST_WDOG3_LEN    1
#define AO_SUBCTRL_ICG_ST_WDOG3_OFFSET 0

#define AO_SUBCTRL_ICG_ST_WDOG4_LEN    1
#define AO_SUBCTRL_ICG_ST_WDOG4_OFFSET 0

#define AO_SUBCTRL_ICG_ST_WDOG5_LEN    1
#define AO_SUBCTRL_ICG_ST_WDOG5_OFFSET 0

#define AO_SUBCTRL_ICG_ST_TIMER0_LEN    1
#define AO_SUBCTRL_ICG_ST_TIMER0_OFFSET 0

#define AO_SUBCTRL_ICG_ST_TIMER1_LEN    1
#define AO_SUBCTRL_ICG_ST_TIMER1_OFFSET 0

#define AO_SUBCTRL_ICG_ST_GICD_LEN    1
#define AO_SUBCTRL_ICG_ST_GICD_OFFSET 0

#define AO_SUBCTRL_ICG_ST_ITS_LEN    1
#define AO_SUBCTRL_ICG_ST_ITS_OFFSET 0

#define AO_SUBCTRL_ICG_ST_APB_MBIGEN_LEN    1
#define AO_SUBCTRL_ICG_ST_APB_MBIGEN_OFFSET 1
#define AO_SUBCTRL_ICG_ST_MBIGEN_LEN        1
#define AO_SUBCTRL_ICG_ST_MBIGEN_OFFSET     0

#define AO_SUBCTRL_ICG_ST_LP_TIMER1_LEN    1
#define AO_SUBCTRL_ICG_ST_LP_TIMER1_OFFSET 0

#define AO_SUBCTRL_ICG_ST_LP_TIMER2_LEN    1
#define AO_SUBCTRL_ICG_ST_LP_TIMER2_OFFSET 0

#define AO_SUBCTRL_ICG_ST_LP_TIMER3_LEN    1
#define AO_SUBCTRL_ICG_ST_LP_TIMER3_OFFSET 0

#define AO_SUBCTRL_ICG_ST_OS_TIMER_LEN    2
#define AO_SUBCTRL_ICG_ST_OS_TIMER_OFFSET 0

#define AO_SUBCTRL_ICG_ST_LP_WDOG_LEN    1
#define AO_SUBCTRL_ICG_ST_LP_WDOG_OFFSET 0

#define AO_SUBCTRL_ICG_ST_IPC_S_LEN    1
#define AO_SUBCTRL_ICG_ST_IPC_S_OFFSET 0

#define AO_SUBCTRL_ICG_ST_IPC_NS_LEN    1
#define AO_SUBCTRL_ICG_ST_IPC_NS_OFFSET 0

#define AO_SUBCTRL_ICG_ST_TRNG_HPRE_LEN    1
#define AO_SUBCTRL_ICG_ST_TRNG_HPRE_OFFSET 1
#define AO_SUBCTRL_ICG_ST_TRNG_LEN         1
#define AO_SUBCTRL_ICG_ST_TRNG_OFFSET      0

#define AO_SUBCTRL_ICG_ST_TIMER2_LEN    1
#define AO_SUBCTRL_ICG_ST_TIMER2_OFFSET 0

#define AO_SUBCTRL_ICG_ST_TIMER3_LEN    1
#define AO_SUBCTRL_ICG_ST_TIMER3_OFFSET 0

#define AO_SUBCTRL_ICG_ST_LP_TIMER0_LEN    1
#define AO_SUBCTRL_ICG_ST_LP_TIMER0_OFFSET 0

#define AO_SUBCTRL_ICG_ST_LSADC_CS_LEN    1
#define AO_SUBCTRL_ICG_ST_LSADC_CS_OFFSET 0

#define AO_SUBCTRL_ICG_ST_PAD_DB_LEN    1
#define AO_SUBCTRL_ICG_ST_PAD_DB_OFFSET 0

#define AO_SUBCTRL_ICG_ST_DJTAG_LEN    1
#define AO_SUBCTRL_ICG_ST_DJTAG_OFFSET 0

#define AO_SUBCTRL_ICG_ST_FUNC_MBIST_LEN    1
#define AO_SUBCTRL_ICG_ST_FUNC_MBIST_OFFSET 0

#define AO_SUBCTRL_ICG_ST_PROBE_LEN    1
#define AO_SUBCTRL_ICG_ST_PROBE_OFFSET 0

#define AO_SUBCTRL_SRST_ST_ITS_LEN    1
#define AO_SUBCTRL_SRST_ST_ITS_OFFSET 0

#define AO_SUBCTRL_SRST_ST_MBIGEN_LEN    1
#define AO_SUBCTRL_SRST_ST_MBIGEN_OFFSET 0

#define AO_SUBCTRL_SRST_ST_GICD_LEN    1
#define AO_SUBCTRL_SRST_ST_GICD_OFFSET 0

#define AO_SUBCTRL_SRST_ST_I2C4_LEN    1
#define AO_SUBCTRL_SRST_ST_I2C4_OFFSET 0

#define AO_SUBCTRL_SRST_ST_I2C5_LEN    1
#define AO_SUBCTRL_SRST_ST_I2C5_OFFSET 0

#define AO_SUBCTRL_SRST_ST_I2C6_LEN    1
#define AO_SUBCTRL_SRST_ST_I2C6_OFFSET 0

#define AO_SUBCTRL_SRST_ST_I2C9_LEN    1
#define AO_SUBCTRL_SRST_ST_I2C9_OFFSET 0

#define AO_SUBCTRL_SRST_ST_SPI_LEN    1
#define AO_SUBCTRL_SRST_ST_SPI_OFFSET 0

#define AO_SUBCTRL_SRST_ST_SMBUS_LEN    1
#define AO_SUBCTRL_SRST_ST_SMBUS_OFFSET 0

#define AO_SUBCTRL_SRST_ST_GPIO_DB_LEN    1
#define AO_SUBCTRL_SRST_ST_GPIO_DB_OFFSET 2
#define AO_SUBCTRL_SRST_ST_GPIO_LEN       2
#define AO_SUBCTRL_SRST_ST_GPIO_OFFSET    0

#define AO_SUBCTRL_SRST_ST_UART_LEN    1
#define AO_SUBCTRL_SRST_ST_UART_OFFSET 0

#define AO_SUBCTRL_SRST_ST_GPIO8_DB_LEN    1
#define AO_SUBCTRL_SRST_ST_GPIO8_DB_OFFSET 1
#define AO_SUBCTRL_SRST_ST_GPIO8_LEN       1
#define AO_SUBCTRL_SRST_ST_GPIO8_OFFSET    0

#define AO_SUBCTRL_SRST_ST_APB_SUBCTRL_LEN    1
#define AO_SUBCTRL_SRST_ST_APB_SUBCTRL_OFFSET 0

#define AO_SUBCTRL_SRST_ST_SYSCNT_LEN    1
#define AO_SUBCTRL_SRST_ST_SYSCNT_OFFSET 0

#define AO_SUBCTRL_SRST_ST_PMCTRL_LEN    1
#define AO_SUBCTRL_SRST_ST_PMCTRL_OFFSET 0

#define AO_SUBCTRL_SRST_ST_PMBUS0_LEN    1
#define AO_SUBCTRL_SRST_ST_PMBUS0_OFFSET 0

#define AO_SUBCTRL_SRST_ST_PMBUS1_LEN    1
#define AO_SUBCTRL_SRST_ST_PMBUS1_OFFSET 0

#define AO_SUBCTRL_SRST_ST_PMPWM_LEN    1
#define AO_SUBCTRL_SRST_ST_PMPWM_OFFSET 0

#define AO_SUBCTRL_SRST_ST_8K_LEN    1
#define AO_SUBCTRL_SRST_ST_8K_OFFSET 0

#define AO_SUBCTRL_SRST_ST_WDOG0_LEN    1
#define AO_SUBCTRL_SRST_ST_WDOG0_OFFSET 0

#define AO_SUBCTRL_SRST_ST_WDOG1_LEN    1
#define AO_SUBCTRL_SRST_ST_WDOG1_OFFSET 0

#define AO_SUBCTRL_SRST_ST_WDOG2_LEN    1
#define AO_SUBCTRL_SRST_ST_WDOG2_OFFSET 0

#define AO_SUBCTRL_SRST_ST_WDOG3_LEN    1
#define AO_SUBCTRL_SRST_ST_WDOG3_OFFSET 0

#define AO_SUBCTRL_SRST_ST_WDOG4_LEN    1
#define AO_SUBCTRL_SRST_ST_WDOG4_OFFSET 0

#define AO_SUBCTRL_SRST_ST_WDOG5_LEN    1
#define AO_SUBCTRL_SRST_ST_WDOG5_OFFSET 0

#define AO_SUBCTRL_SRST_ST_TIMER0_LEN    1
#define AO_SUBCTRL_SRST_ST_TIMER0_OFFSET 0

#define AO_SUBCTRL_SRST_ST_TIMER1_LEN    1
#define AO_SUBCTRL_SRST_ST_TIMER1_OFFSET 0

#define AO_SUBCTRL_SRST_ST_TIMER2_LEN    1
#define AO_SUBCTRL_SRST_ST_TIMER2_OFFSET 0

#define AO_SUBCTRL_SRST_ST_TIMER3_LEN    1
#define AO_SUBCTRL_SRST_ST_TIMER3_OFFSET 0

#define AO_SUBCTRL_SRST_ST_LP_TIMER0_LEN    1
#define AO_SUBCTRL_SRST_ST_LP_TIMER0_OFFSET 0

#define AO_SUBCTRL_SRST_ST_LP_TIMER1_LEN    1
#define AO_SUBCTRL_SRST_ST_LP_TIMER1_OFFSET 0

#define AO_SUBCTRL_SRST_ST_LP_TIMER2_LEN    1
#define AO_SUBCTRL_SRST_ST_LP_TIMER2_OFFSET 0

#define AO_SUBCTRL_SRST_ST_LP_TIMER3_LEN    1
#define AO_SUBCTRL_SRST_ST_LP_TIMER3_OFFSET 0

#define AO_SUBCTRL_SRST_ST_OS_TIMER_LEN    2
#define AO_SUBCTRL_SRST_ST_OS_TIMER_OFFSET 0

#define AO_SUBCTRL_SRST_ST_LP_WDOG_LEN    1
#define AO_SUBCTRL_SRST_ST_LP_WDOG_OFFSET 0

#define AO_SUBCTRL_SRST_ST_IPC_S_LEN    1
#define AO_SUBCTRL_SRST_ST_IPC_S_OFFSET 0

#define AO_SUBCTRL_SRST_ST_IPC_NS_LEN    1
#define AO_SUBCTRL_SRST_ST_IPC_NS_OFFSET 0

#define AO_SUBCTRL_SRST_ST_TRNG_HPRE_LEN    1
#define AO_SUBCTRL_SRST_ST_TRNG_HPRE_OFFSET 1
#define AO_SUBCTRL_SRST_ST_TRNG_LEN         1
#define AO_SUBCTRL_SRST_ST_TRNG_OFFSET      0

#define AO_SUBCTRL_SRST_ST_BISR_S_POWER_LEN    1
#define AO_SUBCTRL_SRST_ST_BISR_S_POWER_OFFSET 0

#define AO_SUBCTRL_SRST_ST_PAD_DB_LEN    1
#define AO_SUBCTRL_SRST_ST_PAD_DB_OFFSET 0

#define AO_SUBCTRL_SRST_ST_DJTAG_LEN    1
#define AO_SUBCTRL_SRST_ST_DJTAG_OFFSET 0

#define AO_SUBCTRL_SRST_ST_FUNC_MBIST_LEN    1
#define AO_SUBCTRL_SRST_ST_FUNC_MBIST_OFFSET 0

#define AO_SUBCTRL_SRST_ST_LSADC_REG7_LEN    1
#define AO_SUBCTRL_SRST_ST_LSADC_REG7_OFFSET 1
#define AO_SUBCTRL_SRST_ST_LSADC_PD_LEN      1
#define AO_SUBCTRL_SRST_ST_LSADC_PD_OFFSET   0

#define AO_SUBCTRL_GIC_NOCMT_IRQ_AND_LEN      1
#define AO_SUBCTRL_GIC_NOCMT_IRQ_AND_OFFSET   2
#define AO_SUBCTRL_GIC_NOCMT_IRQ_OR_LEN       1
#define AO_SUBCTRL_GIC_NOCMT_IRQ_OR_OFFSET    1
#define AO_SUBCTRL_GIC_NOCMT_RST_OUT_N_LEN    1
#define AO_SUBCTRL_GIC_NOCMT_RST_OUT_N_OFFSET 0

#define AO_SUBCTRL_PMBUS_CMD_FINISH_ERR_LEN    1
#define AO_SUBCTRL_PMBUS_CMD_FINISH_ERR_OFFSET 4
#define AO_SUBCTRL_PMBUS_CMD_FINISH_LEN        1
#define AO_SUBCTRL_PMBUS_CMD_FINISH_OFFSET     3
#define AO_SUBCTRL_RX_FIFO_STATUS_LEN          1
#define AO_SUBCTRL_RX_FIFO_STATUS_OFFSET       2
#define AO_SUBCTRL_TX_FIFO_STATUS_LEN          1
#define AO_SUBCTRL_TX_FIFO_STATUS_OFFSET       1
#define AO_SUBCTRL_PMBUS_IF_BUSY_LEN           1
#define AO_SUBCTRL_PMBUS_IF_BUSY_OFFSET        0

#define AO_SUBCTRL_LSADC0_DOUT_LEN             10
#define AO_SUBCTRL_LSADC0_DOUT_OFFSET          8
#define AO_SUBCTRL_LSADC0_CONV_END_FLAG_LEN    1
#define AO_SUBCTRL_LSADC0_CONV_END_FLAG_OFFSET 0

#define AO_SUBCTRL_LSADC1_DOUT_LEN             10
#define AO_SUBCTRL_LSADC1_DOUT_OFFSET          8
#define AO_SUBCTRL_LSADC1_CONV_END_FLAG_LEN    1
#define AO_SUBCTRL_LSADC1_CONV_END_FLAG_OFFSET 0

#define AO_SUBCTRL_HISS_SYSTEM_STATE_LEN    32
#define AO_SUBCTRL_HISS_SYSTEM_STATE_OFFSET 0

#define AO_SUBCTRL_HISS_CORE_STATE_LEN    32
#define AO_SUBCTRL_HISS_CORE_STATE_OFFSET 0

#define AO_SUBCTRL_PAD_TAISHAN_SPI_MD_LEN         1
#define AO_SUBCTRL_PAD_TAISHAN_SPI_MD_OFFSET      20
#define AO_SUBCTRL_PAD_PRB_MUX_SEL_1_LEN          1
#define AO_SUBCTRL_PAD_PRB_MUX_SEL_1_OFFSET       19
#define AO_SUBCTRL_PAD_PRB_MUX_SEL_0_LEN          1
#define AO_SUBCTRL_PAD_PRB_MUX_SEL_0_OFFSET       18
#define AO_SUBCTRL_PAD_PRB_MODE_LEN               1
#define AO_SUBCTRL_PAD_PRB_MODE_OFFSET            17
#define AO_SUBCTRL_PAD_POWERON_BIST_BYPASS_LEN    1
#define AO_SUBCTRL_PAD_POWERON_BIST_BYPASS_OFFSET 16
#define AO_SUBCTRL_PAD_PCIE_RC_EP_MD_LEN          1
#define AO_SUBCTRL_PAD_PCIE_RC_EP_MD_OFFSET       15
#define AO_SUBCTRL_PAD_MDC_DC_MD1_LEN             1
#define AO_SUBCTRL_PAD_MDC_DC_MD1_OFFSET          14
#define AO_SUBCTRL_PAD_MDC_DC_MD0_LEN             1
#define AO_SUBCTRL_PAD_MDC_DC_MD0_OFFSET          13
#define AO_SUBCTRL_PAD_DDR_TRAP2_LEN              1
#define AO_SUBCTRL_PAD_DDR_TRAP2_OFFSET           12
#define AO_SUBCTRL_PAD_DDR_TRAP1_LEN              1
#define AO_SUBCTRL_PAD_DDR_TRAP1_OFFSET           11
#define AO_SUBCTRL_PAD_DDR_TRAP0_LEN              1
#define AO_SUBCTRL_PAD_DDR_TRAP0_OFFSET           10
#define AO_SUBCTRL_PAD_BOOT_SEL2_LEN              1
#define AO_SUBCTRL_PAD_BOOT_SEL2_OFFSET           8
#define AO_SUBCTRL_PAD_BOOT_SEL1_LEN              1
#define AO_SUBCTRL_PAD_BOOT_SEL1_OFFSET           7
#define AO_SUBCTRL_PAD_BOOT_SEL0_LEN              1
#define AO_SUBCTRL_PAD_BOOT_SEL0_OFFSET           6
#define AO_SUBCTRL_PAD_BOOT_SEL_IN_LEN            1
#define AO_SUBCTRL_PAD_BOOT_SEL_IN_OFFSET         5
#define AO_SUBCTRL_PAD_BOOT_CFG4_LEN              1
#define AO_SUBCTRL_PAD_BOOT_CFG4_OFFSET           4
#define AO_SUBCTRL_PAD_BOOT_CFG3_LEN              1
#define AO_SUBCTRL_PAD_BOOT_CFG3_OFFSET           3
#define AO_SUBCTRL_PAD_BOOT_CFG1_LEN              1
#define AO_SUBCTRL_PAD_BOOT_CFG1_OFFSET           1
#define AO_SUBCTRL_PAD_BOOT_CFG0_LEN              1
#define AO_SUBCTRL_PAD_BOOT_CFG0_OFFSET           0

#define AO_SUBCTRL_PAD_TRAP_RSV15_LEN    1
#define AO_SUBCTRL_PAD_TRAP_RSV15_OFFSET 15
#define AO_SUBCTRL_PAD_TRAP_RSV14_LEN    1
#define AO_SUBCTRL_PAD_TRAP_RSV14_OFFSET 14
#define AO_SUBCTRL_PAD_TRAP_RSV13_LEN    1
#define AO_SUBCTRL_PAD_TRAP_RSV13_OFFSET 13
#define AO_SUBCTRL_PAD_TRAP_RSV12_LEN    1
#define AO_SUBCTRL_PAD_TRAP_RSV12_OFFSET 12
#define AO_SUBCTRL_PAD_TRAP_RSV11_LEN    1
#define AO_SUBCTRL_PAD_TRAP_RSV11_OFFSET 11
#define AO_SUBCTRL_PAD_TRAP_RSV10_LEN    1
#define AO_SUBCTRL_PAD_TRAP_RSV10_OFFSET 10
#define AO_SUBCTRL_PAD_TRAP_RSV9_LEN     1
#define AO_SUBCTRL_PAD_TRAP_RSV9_OFFSET  9
#define AO_SUBCTRL_PAD_TRAP_RSV8_LEN     1
#define AO_SUBCTRL_PAD_TRAP_RSV8_OFFSET  8
#define AO_SUBCTRL_PAD_TRAP_RSV7_LEN     1
#define AO_SUBCTRL_PAD_TRAP_RSV7_OFFSET  7
#define AO_SUBCTRL_PAD_TRAP_RSV6_LEN     1
#define AO_SUBCTRL_PAD_TRAP_RSV6_OFFSET  6
#define AO_SUBCTRL_PAD_TRAP_RSV5_LEN     1
#define AO_SUBCTRL_PAD_TRAP_RSV5_OFFSET  5
#define AO_SUBCTRL_PAD_TRAP_RSV4_LEN     1
#define AO_SUBCTRL_PAD_TRAP_RSV4_OFFSET  4
#define AO_SUBCTRL_PAD_TRAP_RSV3_LEN     1
#define AO_SUBCTRL_PAD_TRAP_RSV3_OFFSET  3
#define AO_SUBCTRL_PAD_TRAP_RSV2_LEN     1
#define AO_SUBCTRL_PAD_TRAP_RSV2_OFFSET  2
#define AO_SUBCTRL_PAD_TRAP_RSV1_LEN     1
#define AO_SUBCTRL_PAD_TRAP_RSV1_OFFSET  1
#define AO_SUBCTRL_PAD_TRAP_RSV0_LEN     1
#define AO_SUBCTRL_PAD_TRAP_RSV0_OFFSET  0

#define AO_SUBCTRL_PAD_UPDATE_MODE_N_LEN    1
#define AO_SUBCTRL_PAD_UPDATE_MODE_N_OFFSET 0

#define AO_SUBCTRL_RST_CNT0_LEN    16
#define AO_SUBCTRL_RST_CNT0_OFFSET 0

#define AO_SUBCTRL_RST_CNT1_LEN    16
#define AO_SUBCTRL_RST_CNT1_OFFSET 0

#define AO_SUBCTRL_RST_CNT2_LEN    16
#define AO_SUBCTRL_RST_CNT2_OFFSET 0

#define AO_SUBCTRL_RST_CNT3_LEN    16
#define AO_SUBCTRL_RST_CNT3_OFFSET 0

#define AO_SUBCTRL_HARD_REPAIR_TIMEOUT_LEN    1
#define AO_SUBCTRL_HARD_REPAIR_TIMEOUT_OFFSET 1
#define AO_SUBCTRL_RST_SRC_FLAG_LEN           1
#define AO_SUBCTRL_RST_SRC_FLAG_OFFSET        0

#define AO_SUBCTRL_MRB_HARD_REPAIR_DONE_LEN    30
#define AO_SUBCTRL_MRB_HARD_REPAIR_DONE_OFFSET 0

#define AO_SUBCTRL_EFUSE_HARD_REPAIR_DONE_LEN           1
#define AO_SUBCTRL_EFUSE_HARD_REPAIR_DONE_OFFSET        8
#define AO_SUBCTRL_EFUSE_HARD_REPAIR_DONE_HISS_LEN      1
#define AO_SUBCTRL_EFUSE_HARD_REPAIR_DONE_HISS_OFFSET   3
#define AO_SUBCTRL_EFUSE_HARD_REPAIR_DONE_EFUSE2_LEN    1
#define AO_SUBCTRL_EFUSE_HARD_REPAIR_DONE_EFUSE2_OFFSET 2
#define AO_SUBCTRL_EFUSE_HARD_REPAIR_DONE_EFUSE1_LEN    1
#define AO_SUBCTRL_EFUSE_HARD_REPAIR_DONE_EFUSE1_OFFSET 1
#define AO_SUBCTRL_EFUSE_HARD_REPAIR_DONE_EFUSE0_LEN    1
#define AO_SUBCTRL_EFUSE_HARD_REPAIR_DONE_EFUSE0_OFFSET 0

#define AO_SUBCTRL_RESET_TYPE_LEN    30
#define AO_SUBCTRL_RESET_TYPE_OFFSET 0

#define AO_SUBCTRL_SYSCTRL_LOCK_LEN    32
#define AO_SUBCTRL_SYSCTRL_LOCK_OFFSET 0

#define AO_SUBCTRL_SYSCTRL_UNLOCK_LEN    32
#define AO_SUBCTRL_SYSCTRL_UNLOCK_OFFSET 0

#define AO_SUBCTRL_IOMUX_TZPC_SEL0_LEN    32
#define AO_SUBCTRL_IOMUX_TZPC_SEL0_OFFSET 0

#define AO_SUBCTRL_IOMUX_TZPC_SEL1_LEN    32
#define AO_SUBCTRL_IOMUX_TZPC_SEL1_OFFSET 0

#define AO_SUBCTRL_PROBE_MUX_SEL_LEN    4
#define AO_SUBCTRL_PROBE_MUX_SEL_OFFSET 0

#define AO_SUBCTRL_SMMU_ICG_EN_SRST_REQ_SEC_ATTR_SWITCHER_LEN    1
#define AO_SUBCTRL_SMMU_ICG_EN_SRST_REQ_SEC_ATTR_SWITCHER_OFFSET 0

#define AO_SUBCTRL_MBIGEN_ICG_EN_SRST_REQ_SEC_ATTR_SWITCHER_LEN    1
#define AO_SUBCTRL_MBIGEN_ICG_EN_SRST_REQ_SEC_ATTR_SWITCHER_OFFSET 0

#define AO_SUBCTRL_ITS_ICG_EN_SRST_REQ_SEC_ATTR_SWITCHER_LEN    1
#define AO_SUBCTRL_ITS_ICG_EN_SRST_REQ_SEC_ATTR_SWITCHER_OFFSET 0

#define AO_SUBCTRL_GICD_ICG_EN_SRST_REQ_SEC_ATTR_SWITCHER_LEN    1
#define AO_SUBCTRL_GICD_ICG_EN_SRST_REQ_SEC_ATTR_SWITCHER_OFFSET 0

#define AO_SUBCTRL_SEC_SWITCH_WDOG0_LEN    1
#define AO_SUBCTRL_SEC_SWITCH_WDOG0_OFFSET 0

#define AO_SUBCTRL_SEC_SWITCH_WDOG1_LEN    1
#define AO_SUBCTRL_SEC_SWITCH_WDOG1_OFFSET 0

#define AO_SUBCTRL_SEC_SWITCH_WDOG2_LEN    1
#define AO_SUBCTRL_SEC_SWITCH_WDOG2_OFFSET 0

#define AO_SUBCTRL_SEC_SWITCH_WDOG3_LEN    1
#define AO_SUBCTRL_SEC_SWITCH_WDOG3_OFFSET 0

#define AO_SUBCTRL_SEC_SWITCH_WDOG4_LEN    1
#define AO_SUBCTRL_SEC_SWITCH_WDOG4_OFFSET 0

#define AO_SUBCTRL_SEC_SWITCH_WDOG5_LEN    1
#define AO_SUBCTRL_SEC_SWITCH_WDOG5_OFFSET 0

#define AO_SUBCTRL_SEC_SWITCH_TIMER0_LEN    1
#define AO_SUBCTRL_SEC_SWITCH_TIMER0_OFFSET 0

#define AO_SUBCTRL_SEC_SWITCH_TIMER1_LEN    1
#define AO_SUBCTRL_SEC_SWITCH_TIMER1_OFFSET 0

#define AO_SUBCTRL_SEC_SWITCH_TIMER2_LEN    1
#define AO_SUBCTRL_SEC_SWITCH_TIMER2_OFFSET 0

#define AO_SUBCTRL_SEC_SWITCH_TIMER3_LEN    1
#define AO_SUBCTRL_SEC_SWITCH_TIMER3_OFFSET 0

#define AO_SUBCTRL_SEC_SWITCH_LP_TIMER0_LEN    1
#define AO_SUBCTRL_SEC_SWITCH_LP_TIMER0_OFFSET 0

#define AO_SUBCTRL_SEC_SWITCH_LP_TIMER1_LEN    1
#define AO_SUBCTRL_SEC_SWITCH_LP_TIMER1_OFFSET 0

#define AO_SUBCTRL_SEC_SWITCH_LP_TIMER2_LEN    1
#define AO_SUBCTRL_SEC_SWITCH_LP_TIMER2_OFFSET 0

#define AO_SUBCTRL_SEC_SWITCH_LP_TIMER3_LEN    1
#define AO_SUBCTRL_SEC_SWITCH_LP_TIMER3_OFFSET 0

#define AO_SUBCTRL_SEC_SWITCH_I2C4_LEN    1
#define AO_SUBCTRL_SEC_SWITCH_I2C4_OFFSET 0

#define AO_SUBCTRL_SEC_SWITCH_I2C5_LEN    1
#define AO_SUBCTRL_SEC_SWITCH_I2C5_OFFSET 0

#define AO_SUBCTRL_SEC_SWITCH_I2C6_LEN    1
#define AO_SUBCTRL_SEC_SWITCH_I2C6_OFFSET 0

#define AO_SUBCTRL_SEC_SWITCH_I2C9_LEN    1
#define AO_SUBCTRL_SEC_SWITCH_I2C9_OFFSET 0

#define AO_SUBCTRL_SEC_SWITCH_LP_PMBUS0_LEN    1
#define AO_SUBCTRL_SEC_SWITCH_LP_PMBUS0_OFFSET 0

#define AO_SUBCTRL_SEC_SWITCH_LP_PMBUS1_LEN    1
#define AO_SUBCTRL_SEC_SWITCH_LP_PMBUS1_OFFSET 0

#define AO_SUBCTRL_SEC_SWITCH_GPIO8_LEN    1
#define AO_SUBCTRL_SEC_SWITCH_GPIO8_OFFSET 0

#define AO_SUBCTRL_SEC_SWITCH_SMBUS_LEN    1
#define AO_SUBCTRL_SEC_SWITCH_SMBUS_OFFSET 0

#define AO_SUBCTRL_SEC_SWITCH_TPM_LEN    1
#define AO_SUBCTRL_SEC_SWITCH_TPM_OFFSET 0

#define AO_SUBCTRL_SEC_SWITCH_TOP2HISS_LEN    1
#define AO_SUBCTRL_SEC_SWITCH_TOP2HISS_OFFSET 0

#define AO_SUBCTRL_SEC_SWITCH_LP2HISS_LEN    1
#define AO_SUBCTRL_SEC_SWITCH_LP2HISS_OFFSET 0

#define AO_SUBCTRL_ECO_RSV0_SUBCTRL_LEN    32
#define AO_SUBCTRL_ECO_RSV0_SUBCTRL_OFFSET 0

#define AO_SUBCTRL_ECO_RSV1_SUBCTRL_LEN    32
#define AO_SUBCTRL_ECO_RSV1_SUBCTRL_OFFSET 0

#define AO_SUBCTRL_ECO_RSV2_SUBCTRL_LEN    32
#define AO_SUBCTRL_ECO_RSV2_SUBCTRL_OFFSET 0

#define AO_SUBCTRL_ECO_RSV3_SUBCTRL_LEN    32
#define AO_SUBCTRL_ECO_RSV3_SUBCTRL_OFFSET 0

#define AO_SUBCTRL_ECO_RSV4_SUBCTRL_LEN    32
#define AO_SUBCTRL_ECO_RSV4_SUBCTRL_OFFSET 0

#define AO_SUBCTRL_ECO_RSV5_SUBCTRL_LEN    32
#define AO_SUBCTRL_ECO_RSV5_SUBCTRL_OFFSET 0

#define AO_SUBCTRL_VER_NUM_LEN    32
#define AO_SUBCTRL_VER_NUM_OFFSET 0

#endif // __AO_SUBCTRL_REG_OFFSET_FIELD_H__
